RTL Engineer Jobs in USA 2026 with Visa Sponsorship

July 3, 2026 5:10 pm

RTL Engineer Jobs in USA 2026 with Visa Sponsorship

This RTL Engineer role focuses on designing and implementing the Register Transfer Level (RTL) architecture for an AI accelerator. The position involves owning the end-to-end digital design of compute datapaths, memory subsystems, on-chip interconnects, and control logic.

The engineer will translate microarchitecture specifications into synthesizable, timing-closed RTL and collaborate across verification, physical design, and DFT teams to ensure silicon readiness. The role also includes participation in architectural decisions, performance trade-offs, and AI-assisted design workflows to improve development efficiency.

About the Hiring Firm

DensityAI is a technology company focused on building advanced AI accelerator hardware. The organization works on high-performance compute systems designed for modern artificial intelligence workloads, leveraging cutting-edge semiconductor design practices. It operates in a fast-paced engineering environment with a strong emphasis on innovation, silicon development, and cross-disciplinary collaboration across architecture, design, and verification teams.

Job Duties

Design and implement RTL for AI accelerator subsystems including datapaths, memory systems, and interconnects.
Translate architectural specifications into synthesizable SystemVerilog RTL meeting power, performance, and area (PPA) targets.
Drive microarchitecture decisions including pipelining, control logic, and power optimization techniques.
Collaborate with verification teams to validate functionality and ensure design correctness.
Work with physical design teams to achieve synthesis, timing closure, and floorplan alignment.
Support DFT activities to ensure testability and manufacturability of silicon designs.
Perform linting, static timing analysis (STA), and constraint development (SDC).
Participate in architecture reviews and debug issues across simulation, emulation, and silicon bring-up.
Develop scripting tools (Python/Tcl) to automate design and verification tasks.

Job Requirements

5+ years of experience in RTL design for complex digital blocks or SoC-level systems.
Strong expertise in SystemVerilog/Verilog RTL development.
Deep understanding of microarchitecture concepts such as pipelining, datapaths, FIFOs, and arbitration.
Experience with synthesis, STA, clock/power gating, and CDC analysis.
Familiarity with RTL-to-GDSII flow and collaboration with DV, PD, and DFT teams.
Proficiency in scripting languages such as Python or Tcl.
Experience with AI/ML accelerators, high-performance compute systems, or low-power design is a plus.
Knowledge of advanced interfaces (e.g., PCIe, HBM, SerDes) is advantageous.

Click Here to Apply

Conclusion

This role offers a high-impact opportunity to contribute to next-generation AI hardware design at silicon level. It is ideal for experienced RTL engineers who want to work on advanced accelerator architectures while collaborating across full-chip development teams in a cutting-edge semiconductor environment.

READ MORE